Conventional CMOS logic gates may be categorized as either static or dynamic gates. In static gates, the actual input logic signals cause the gate to switch. Clocked signals such as set or reset signals are not required in a static gate. On the other hand, dynamic gates require a set or reset signal and accompanying logic. Dynamic gates are often faster than static gates. However, additional complexities associated with clocked inputs and power consumption must be overcome in dynamic gates. For example, clocked input gates require synchronized inputs and generally consume more power than static gates.
Challenges associated with dynamic logic gates are especially evident in CMOS exclusive-OR (XOR) gates. Compared with other basic logic gates, conventional CMOS XOR gates are slow and power-hungry. Conventional CMOS XOR gates contain a large number of transistors. The resultant large circuit footprint and fan-out, which affect input timing for successive XOR stages, causes relatively slow circuit speeds. Additionally, the large size of the CMOS transistors used in an XOR gate, coupled with the large fan-out, creates a large amount of capacitance that must be switched each time the XOR gate switches. The switching of large capacitance increases power consumption and also results in relatively slow XOR gate switching.
A type of dynamic XOR gate is a precharge/evaluate gate. In precharge/evaluate gates, gate outputs are charged during a precharge mode prior to evaluation of the logic input signals during an evaluation mode. Typically, a precharge unit includes at least one of a class of transistors (for example, a PMOS transistor) such that the precharge unit turns on when the associated clock signal is either high or low (a PMOS transistor, for example, will turn on when the input clock signal switches low). In contrast, an evaluation unit includes transistors that are off when the precharge transistors are on. For example, if the precharge transistors were PMOS transistors, the evaluate transistors would be NMOS transistors that would turn on when the input clock signal switched high. Thus, when the precharge/evaluate XOR gate is in the precharge mode, outputs from the evaluation unit are set “high” and the evaluation unit is not active (because the evaluation transistors are not on). When the clock signal transitions to a low state, the precharge unit turns off and the evaluation unit turns on allowing the evaluation unit to output the result of the logic operation.
One challenge associated with precharge/evaluate XOR gates is that XOR gates are often linked together in a chain of successive XOR gates. Setting the outputs of a linked evaluation unit high could erroneously provide input to another XOR gate in the chain.
An additional challenge in implementing a precharge/evaluate gate is minimizing power consumption during a standby mode. For example, DRAM (dynamic random access memory) memory devices typically have a low-power or standby specification requiring the DRAM to operate within a maximum current during a low-power or standby mode. Since DRAM memory cells must be refreshed during the lower-power or standby mode, reducing the frequency of the refresh operations will improve the DRAM's operational performance for the mode. During a standby mode, a precharge/evaluation XOR gate is inactive and ideally has a zero standby current (and hence, zero power consumption). However, in reality, various leak currents across the transistors in the XOR gate combine to result in significant power consumption even though the logic gate is “inactive.” In response to the undesired power drain, conventional XOR gates have utilized large external p-channel local regulator devices for the purpose of bringing the gate standby current Ioff to near zero. Using large p-channel local regulator devices compromises circuit speed, however, as a result of the resultant decrease in overall power supply voltage.
Thus, an XOR gate with efficient switching speeds and low power consumption is desirable. An XOR gate that implements an efficient method of reducing standby current is also desirable.